By Connor Horn
September 11, 2026
Why can’t we just put everything on one chip?
A semiconductor computing system is like a microscopic workplace. A workplace where countless employees are doing domain-specific jobs, but all deeply interconnected to create some valuable output. The workplace might be spread out in different buildings across a wide campus, or perhaps it might be occupying many consecutive floors of a skyscraper. Often it is a combination of both, depending on the cost of real estate and how particular the workspace needs to be (a specific factory layout for manufacturing versus generic offices for the sales team). For the layout of semiconductor computing chips, the ultra-dense skyscraper has become highly preferable to the sprawling campus because (1) silicon real estate is getting scarce and (2) the time information takes to travel across separate chips is becoming a massive hindrance.
Consider the Apple M1 chip. Announced in November 2020, it put sixteen billion transistors on a single silicon chip of roughly 120 mm2 at TSMC’s 5 nm node: an eight-core CPU, an integrated GPU, a 16-core Neural Engine, image signal processing, media encode and decode, and the Secure Enclave. Around it, on the same package substrate, Apple placed LPDDR4X in a unified memory pool that the CPU, GPU, and Neural Engine could all address without copying data between them [1].
Every one of those blocks had been a separate chip, or a separate card, in the not-too-distant past. The semiconductor industry has continued in the same direction with more accelerator blocks, more memory bandwidth, and more of the system pulled inside the package boundary. There are, however, components that the monolithic package has never managed to absorb. The laser that lights every optical link in a datacenter is still a dedicated InP die. The isolator protecting the laser is still a separately assembled iron garnet. The power converters feeding the accelerator are still discrete units, especially as the industry moves to GaN and SiC. The heat those parts generate is still spread by materials nobody can get into the package. By now the thread is obvious: these are all non-silicon semiconductors. Their properties are necessary for modern high-performance computing architectures, and in their current discrete form they seriously constrain data transfer, power density, and heat dissipation.
The next round of integration cannot be done the old way. Pulling the laser, isolator, power stage, and heat spreader inside the package means combining all these other semiconductors alongside the silicon. Those crystals all come as expensive, small-diameter boules sliced into 350-700 µm thick wafers, which need to be fabricated using material-specific procedures. Thus far it has been an intractable challenge to efficiently get these components onto the silicon package. The IEEE Heterogeneous Integration Roadmap [2] and a 2026 perspective led by Intel [3] argue that heterogeneous integration is now a critical load-bearing mechanism for continued progress and note that industry roadmaps have not kept pace.
First, let’s come up with a wish list of exactly what we want, and then talk about what K1 Semiconductor is doing to get there.
What would you integrate into a silicon compute package if manufacturability were no object?
Critical field → GaN, SiC, and Ga₂O₃
A modern accelerator draws ~a thousand amps at <1 volt through package planes, vias, and board copper. Because Joule heating power loss in that path scales with the square of the current, the natural fix is to deliver the power at higher voltage and lower current until right before it reaches the compute layer. Ideally, we want to put the final conversion stage inside the package, directly beneath the die.
Gallium nitride has a critical field near 3.3 MV/cm against silicon’s 0.3 MV/cm, so it can be more heavily doped and much thinner as a power conversion device. GaN also combines low switching charge and capacitance with low on-resistance, allowing power conversion at higher frequencies and thus smaller passive components. Intel has been exploring an on-package 48 V-to-6 V intermediate-bus converter built on low-voltage GaN power transistors, reaching 96.1% peak efficiency and 6.8 kW/in3 of power density [4]. The natural next step is to move the GaN devices still closer to the compute die through layer transfer and heterogeneous integration techniques.
Upstream, conversion from several thousand volts favors silicon carbide, and the wishlist entry beyond it is β-Ga2O3 (gallium oxide), with a 4.8 eV bandgap and a projected critical field near 8 MV/cm [5]. Its exceptional breakdown properties are offset by extremely poor thermal conductivity, making self-heating one of the principal obstacles to high-power operation. A promising architecture is therefore a micron-scale β-Ga2O3 membrane bonded to a high-thermal-conductivity host such as SiC or diamond [6], allowing the electrical device to exploit Ga2O3 while moving heat through another material. This kind of structure is an important use case for layer transfer as well, because the active crystal is retained only where its electronic properties are needed, while the bulk substrate beneath it is replaced by a material chosen for thermal transport.
Crystal asymmetry → LiNbO3 and BaTiO3
Today, modulation inside a silicon photonic engine is done by the silicon itself using free-carrier plasma dispersion, where carrier injection or depletion shifts the refractive index. Silicon’s structure has inversion symmetry, so there is no linear electro-optic (Pockels) effect. The resulting index shift is relatively weak, so designers often wrap the modulator into a ring resonator to enhance it. Free-carrier modulation also introduces optical loss and unwanted amplitude modulation. Meanwhile, the ring resonance is temperature-sensitive and needs a resistive heater to hold it on wavelength, costing 20-30 mW continuously.
A transferred lithium niobate chiplet replaces that arrangement and can do at least three further jobs. It modulates by the Pockels effect with no carriers and no absorption penalty: r33 ≈ 30.8 pm/V at bandwidths past 100 GHz. It tunes those same rings at nanowatts of static power instead of tens of milliwatts [7]. Driven via RF at a microring’s free spectral range, the LiNbO3 generates a frequency comb, turning one laser pump into tens of evenly spaced lines and breaking the one-laser-per-channel arrangement that dominates the optical engine’s cost and failure rate [8]. And doped with erbium in the melt, it amplifies: Er:LiNbO3 waveguides have reached 38 dB of internal net gain in a ~9 cm spiral [9], replacing a component that today lives in a box outside the system. On the horizon is BaTiO3, whose Pockels coefficient can be an order of magnitude larger still: r42 has been measured near 923 pm/V, potentially enabling the same modulation and tuning functions in much smaller devices and at lower drive voltages [10].
Direct bandgap → InP
Silicon does not lase, so silicon photonic engines typically use a bulky III-V laser die and flip-chip bond it onto the silicon. That coupling is a mechanical alignment between two waveguides whose modes do not match: on the order of a micron at the III-V facet against a few hundred nanometers in the silicon. In a recent example, ±0.5 µm of lateral misalignment costs about 1 dB, while the same error vertically costs 6.35 dB (>75% of the light) [11].
Using layer transfer to integrate the III-V film onto the photonic wafer replaces mechanical alignment with lithographic alignment. When the III-V film is patterned after bonding, vertical position is set by layer thickness and lateral position by mask overlay, both with nanometer precision. At present, alignment is serial and per-die, whereas a bonded film is one step for every laser on the wafer at once.
InP also has a low thermal conductivity and should ideally be integrated with a heat spreader such as a layer of SiC or diamond, realizing another advantageous use for chiplet integration. This is especially important because InP’s threshold current and emission wavelength are strongly temperature-dependent, and a nearby heat spreader would keep the emission wavelength constant and reliable even at high powers.
Thermal conductivity → diamond
Silicon conducts heat at roughly 150 W/m·K; 4H-SiC does 370-490; single-crystal diamond exceeds 2000. As a base layer, it can host a GaN, Ga2O3, or InP device, rapidly spreading heat away from the high-power hotspots. As an interior tier, diamond films may sit in the middle sections of a 3D stack so that the heat can exit laterally instead of crossing the many tiers above or below. A 20 µm diamond layer bonded between tiers, carrying vias for signal and power, gives that heat a lateral escape at 2000 W/m·K instead of forcing it through silicon at 150.
What is K1 Semiconductor doing to enable this?
Notice what every one of the wish list materials has in common. None of them wants a wafer. All of them want a film that is thin enough to sit inside a package’s vertical budget, flat enough to bond, and is high-quality to build a device on. Through-film vias at 20 µm are a shallow etch at a comfortable aspect ratio rather than a >100 µm deep reactive-ion etch. Every material on that list can be grown today; the missing piece is the form factor.
However, a thin form factor alone isn’t sufficient. The thin films need to be able to be put through epitaxial growth, implantation, etching, polishing, and other fabrication steps, and then somehow get transplanted onto a super-complicated heterogeneous stack of silicon and other semiconductor devices. Essentially, we want to use all the fab expertise that has been learned in manufacturing discrete components and then pop off the active layers as thin films and deliver them onto the compute system.
At K1 Semiconductor, our thesis is to build engineered semiconductor wafers in which the thin non-silicon semiconductor layer is bonded to a compatible carrier, such that it looks and behaves like a full wafer during device fabrication, but then the layer can be released from its carrier to take on the desired thin form factor for heterogeneous integration into the silicon package. Fabs make devices on our wafers (with no special tooling needed!) and then can release and transfer the known-good dies onto their final platform.
Logistically, we propose the use of our proprietary wafer splitting process to efficiently create these engineered wafers with a built-in release mechanism and ship them to device manufacturers for all of the fabrication and packaging. This allows K1 to serve as an upstream material supplier, rather than a cog that has to fit within a thousand-step manufacturing process. We can co-develop with fab partners and quickly customize different wafer structures for them with our in-house expertise. Different materials, different thicknesses, and different release mechanisms are all possible. Whereas other heterogeneous integration solutions are typically built for one specific architecture that will become outdated with subsequent generations, the customization aspect of our offering remains resilient to future change. No longer will thermal budget constrain the hundreds of steps after a heteroepitaxial or ion-implanted layer is appended to the silicon before the device is complete. Our product is built to be modular and agnostic to whatever behemoth of semiconductor compute package awaits us in the years to come.
K1 Semiconductor builds engineered substrates for three-dimensional heterogeneous integration: wafer splitting of SiC, GaN, InP, LiNbO3, diamond, and other semiconductor crystals into <50 µm thick bulk-quality layers, carried on a releasable handle substrate that fabs can process.
References
[1] “Apple unleashes M1,” Apple Newsroom. Accessed: Aug. 30, 2026. [Online]. Available: https://www.apple.com/newsroom/2020/11/apple-unleashes-m1/
[2] “2025 Edition – IEEE Electronics Packaging Society.” Accessed: Aug. 30, 2026. [Online]. Available: https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2025-edition/
[3] R. V. Mahajan et al., “The heterogeneous integration of electronic components,” Nat. Rev. Electr. Eng., vol. 3, no. 4, pp. 254–263, Apr. 2026, doi: 10.1038/s44287-026-00270-1.
[4] M. Khatua et al., “A 96.1% Peak Efficiency, 6.8 kW/in3, 48V-to-6V On-package Intermediate Bus Converter with LV-GaN Power Transistors,” in 2025 IEEE Applied Power Electronics Conference and Exposition (APEC), Mar. 2025, pp. 1681–1686. doi: 10.1109/APEC48143.2025.10977473.
[5] S. Sun, C. Wang, S. Alghamdi, H. Zhou, Y. Hao, and J. Zhang, “Recent Advanced Ultra-Wide Bandgap β-Ga2O3 Material and Device Technologies,” Adv. Electron. Mater., vol. 11, no. 1, p. 2300844, Jan. 2025, doi: 10.1002/aelm.202300844.
[6] Z. Cheng, L. Yates, J. Shi, M. J. Tadjer, K. D. Hobart, and S. Graham, “Thermal conductance across β-Ga2O3-diamond van der Waals heterogeneous interfaces,” APL Mater., vol. 7, no. 3, p. 031118, Mar. 2019, doi: 10.1063/1.5089559.
[7] Z. Wang et al., “Fast-speed and low-power-consumption optical phased array based on lithium niobate waveguides,” Nanophotonics, vol. 13, no. 13, pp. 2429–2436, 2024, doi: 10.1515/nanoph-2024-0066.
[8] M. Zhang et al., “Broadband electro-optic frequency comb generation in a lithium niobate microring resonator,” Nature, vol. 568, no. 7752, pp. 373–377, Apr. 2019, doi: 10.1038/s41586-019-1008-7.
[9] Y. Wang et al., “Unifying optical gain and electro-optical dynamics in Er-doped thin-film lithium niobate platform,” Nat. Commun., vol. 16, no. 1, p. 10462, Nov. 2025, doi: 10.1038/s41467-025-65460-1.
[10] S. Abel et al., “Large Pockels effect in micro- and nanostructured barium titanate integrated on silicon,” Nat. Mater., vol. 18, no. 1, pp. 42–47, Jan. 2019, doi: 10.1038/s41563-018-0208-0.
[11] J. Wang et al., “Scalable single-microring hybrid III-V/Si lasers for emerging narrow-linewidth applications,” Opt. Express, vol. 32, no. 15, pp. 26751–26762, Jul. 2024, doi: 10.1364/OE.529952.